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| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 19:40:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-04 20:33:07 +0000 |
| commit | c07f8fbe6fd13e4245da71574b52b47e9733db84 (patch) | |
| tree | 12db8b3c40552eab81045c6165538e2d3ba36ce8 /src/cpu | |
| parent | 961d31bdb3c97e177156ed335d6f2c726d08ab51 (diff) | |
| download | coreboot-c07f8fbe6fd13e4245da71574b52b47e9733db84.tar.xz | |
security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 6d9fbc4a0b..1c293d4647 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -42,7 +42,7 @@ #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/me.h" -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> static inline void reset_system(void) { @@ -245,8 +245,8 @@ void romstage_common(const struct romstage_params *params) romstage_handoff_init(wake_from_s3); post_code(0x3f); - if (IS_ENABLED(CONFIG_LPC_TPM)) - init_tpm(wake_from_s3); + if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) + tpm_setup(wake_from_s3); } asmlinkage void romstage_after_car(void) |