diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-04-12 09:50:53 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-04-12 09:50:53 +0000 |
| commit | f1ce6f2c2518b70eae23502593393fd40fd73806 (patch) | |
| tree | 43c71d9fc743199cc57d862ae3e1f4dc5a3c6930 /src/cpu | |
| parent | d9466493ec85045659336d11868ddd626944b650 (diff) | |
| download | coreboot-f1ce6f2c2518b70eae23502593393fd40fd73806.tar.xz | |
- move the XIP_ROM_* flags to src/cpu/x86/Kconfig exclusively
- set them to span the last 64k, instead of the last 128k
by default
- fixes via CAR for tiny bootblock
- enabled tiny bootblock for via/vt8454c
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 6 | ||||
| -rw-r--r-- | src/cpu/x86/Kconfig | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 7eb85333ac..c926ab6f91 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -139,7 +139,7 @@ clear_fixed_var_mtrr_out: xorl $0x5c5c5c5c,%eax rep stosl - movl CONFIG_XIP_ROM_BASE, %esi + movl REAL_XIP_ROM_BASE, %esi movl %esi, %edi movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx rep lodsl @@ -241,10 +241,10 @@ testok: movb $0x40,%al movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax wrmsr - /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */ + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl $0x206, %ecx xorl %edx, %edx - movl $CONFIG_XIP_ROM_BASE,%eax + movl $REAL_XIP_ROM_BASE,%eax orl $(0 | 6), %eax wrmsr diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 59f27de794..325991e28e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -25,8 +25,8 @@ config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 config XIP_ROM_BASE hex - default 0xfffe0000 + default 0xffff0000 config XIP_ROM_SIZE hex - default 0x20000 + default 0x10000 |