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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 17:23:12 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-20 19:01:05 +0000
commit24284270c73ba4e35af10ea9054f084c989dff52 (patch)
treee9a61270217da63a4ca1e849c1dee7cda0fadd58 /src/cpu
parentecebee0561cf3e06bfba55509a5b7bebdb54d998 (diff)
downloadcoreboot-24284270c73ba4e35af10ea9054f084c989dff52.tar.xz
sb/amd/sb700: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/family_10h-family_15h/init_cpus.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 452f7ce3fd..89188fddd7 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -30,10 +30,6 @@
#include <southbridge/amd/common/reset.h>
-#if CONFIG(SOUTHBRIDGE_AMD_SB700)
-#include <southbridge/amd/sb700/sb700.h>
-#endif
-
#if CONFIG(SOUTHBRIDGE_AMD_SB800)
#include <southbridge/amd/sb800/sb800.h>
#endif
@@ -1045,7 +1041,7 @@ void cpuSetAMDMSR(uint8_t node_id)
}
}
-#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(MSR_INTPEND);