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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-25 16:03:12 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-03 08:09:32 +0100
commit4ee82c69a2ecfe1afc9a357fc7ddbaa06c10d2b5 (patch)
tree5c0d8f8d12934e9b136a2b7993108d2b1271ede2 /src/cpu
parent34ad72cd03923461d1a2cd80c798002e94f92069 (diff)
downloadcoreboot-4ee82c69a2ecfe1afc9a357fc7ddbaa06c10d2b5.tar.xz
AGESA fam16kb: Move clearing of NoSnoopEnable bit
Originally from commit 4ca72139 move this code now from cpu/ to northbridge/. Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7603 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/agesa/amd_late_init.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index a0a3516835..26442f4913 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -19,10 +19,6 @@
#include <arch/acpi.h>
#include <bootstate.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
@@ -38,20 +34,6 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
- device_t dev;
- u32 value;
- dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
- pci_write_config32(dev, 0xF8, 0);
- pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
-
- /* disable No Snoop */
- dev = dev_find_slot(0, PCI_DEVFN(1, 1));
- value = pci_read_config32(dev, 0x60);
- value &= ~(1 << 11);
- pci_write_config32(dev, 0x60, value);
-#endif
-
#if CONFIG_AMD_SB_CIMX
sb_Late_Post();
#endif