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authorStefan Reinauer <reinauer@chromium.org>2013-05-06 18:05:39 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-05-08 18:24:23 +0200
commit648d16679c5cf4f91c9f8b48ee77c6a9ada87523 (patch)
treef2985f2e7e1cdf4a51897ccb30d6b4f2da6272f0 /src/cpu
parent2a3c10677f354f660a759d47a3b26b1d8818e76c (diff)
downloadcoreboot-648d16679c5cf4f91c9f8b48ee77c6a9ada87523.tar.xz
copy_and_run: drop boot_complete parameter
Since this parameter is not used anymore, drop it from all calls to copy_and_run() Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/cpu/amd/geode_gx2/cache_as_ram.inc4
-rw-r--r--src/cpu/amd/geode_lx/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc5
-rw-r--r--src/cpu/intel/haswell/romstage.c2
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc5
-rw-r--r--src/cpu/via/car/cache_as_ram.inc5
9 files changed, 2 insertions, 35 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 861948ff57..68e7c09ad3 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -165,7 +165,7 @@ static void post_cache_as_ram(void)
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute coreboot_ram */
- copy_and_run(0);
+ copy_and_run();
/* We will not return */
print_debug("should not be here -\n");
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 941d507f9c..6a107fe5f1 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -182,8 +182,6 @@ done_cache_as_ram_main:
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0
- /* clear boot_complete flag */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
@@ -197,8 +195,6 @@ __main:
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
- movl %ebp, %esi
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index 3146fd296c..d2c241565e 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -208,8 +208,6 @@ done_cache_as_ram_main:
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0
- /* clear boot_complete flag */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
@@ -223,8 +221,6 @@ __main:
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
- movl %ebp, %esi
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 781e48017b..1ea50b8b37 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -357,17 +357,12 @@ lout:
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
- /* Clear boot_complete flag. */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl %ebp, %esi
-
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 9ef69adfcb..8a845e954a 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -431,17 +431,12 @@ no_msr_11e:
post_code(0x3c)
- /* Clear boot_complete flag. */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl %ebp, %esi
-
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 077e409a5e..1093e6b1e5 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -326,7 +326,7 @@ void romstage_after_car(void)
#endif
/* Load the ramstage. */
- copy_and_run(0);
+ copy_and_run();
}
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 4202da9800..2652cb7433 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -316,17 +316,12 @@ __acpi_resume_backup_done:
post_code(0x3d)
- /* Clear boot_complete flag. */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl %ebp, %esi
-
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index b8222e15a2..50fab35ccc 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -225,17 +225,12 @@ clear_mtrrs:
post_code(0x3c)
- /* Clear boot_complete flag. */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl %ebp, %esi
-
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
call copy_and_run
.Lhlt:
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 1af8eccfe1..17b4b833db 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -264,17 +264,12 @@ testok:
movl %eax, %cr0
invd
- /* Clear boot_complete flag. */
- xorl %ebp, %ebp
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl %ebp, %esi
-
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
call copy_and_run
.Lhlt: