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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-07-10 13:24:29 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-25 01:17:26 +0200 |
| commit | 8d32b89fa4ea30aa57b578d79bc656c9e6545795 (patch) | |
| tree | cb98f55e18c57ad4893768aaf977623d356c5280 /src/cpu | |
| parent | f4d362339f4d96657be1dc5956c34278d1089eba (diff) | |
| download | coreboot-8d32b89fa4ea30aa57b578d79bc656c9e6545795.tar.xz | |
Fix LAPIC timer on Ivy Bridge systems
The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy
Bridge systems. However, the current timer code assumed that the clock
would run at 200MHz instead. This made all delays twice as long as
needed.
Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1330
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 1fd0c60234..562c79c2e8 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -50,6 +50,7 @@ static int set_timer_fsb(void) timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ timer_fsb = 100; break; default: |