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authorVadim Bendebury <vbendeb@chromium.org>2012-06-19 04:20:20 +0000
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:15:35 +0200
commit999e94cb7a428751cf11be6859dbf29f954bbdc3 (patch)
tree7ae532eb3d43966f57be31f299886751ddf5d646 /src/cpu
parent48c6bae1f2cc1dc1996c36986b7a87273f48b64e (diff)
downloadcoreboot-999e94cb7a428751cf11be6859dbf29f954bbdc3.tar.xz
Config changes to support microcode in CBFS
Nothing is yet enabled, this is just a config skeleton change. The MICROCODE_INCLUDE_PATH definition is going to be used by the Makefile building the microcode blob for CBFS inclusion. Change-Id: I7868db3cfd4b181500e361706e5f4dc08ca1c87d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1292 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/Kconfig9
-rw-r--r--src/cpu/intel/model_206ax/Kconfig6
2 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index d34b1abe30..f37bbf6755 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,4 +62,13 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
+if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
+
+config MICROCODE_IN_CBFS
+ bool "Look for microcode in CBFS"
+ help
+ Load microcode updates from CBFS instead of compiling them in.
+
+endif
+
endif # ARCH_X86
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6c709937c9..1d4ff02b36 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -21,6 +21,12 @@ config SMM_TSEG_SIZE
hex
default 0x800000
+if MICROCODE_IN_CBFS
+config MICROCODE_INCLUDE_PATH
+ string
+ default "src/cpu/intel/model_206ax"
+endif
+
endif
if CPU_INTEL_MODEL_206AX