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| author | Myles Watson <mylesgw@gmail.com> | 2009-04-27 16:08:26 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-04-27 16:08:26 +0000 |
| commit | bc9de2f1e2b9582f0bd692ef3b8f3cc98d32bfb5 (patch) | |
| tree | 38612942afc7c932b5b45b5b03c3c09c4fd2f553 /src/cpu | |
| parent | 0d6ce50a1e76a59cdadf47a1d3770fb061353906 (diff) | |
| download | coreboot-bc9de2f1e2b9582f0bd692ef3b8f3cc98d32bfb5.tar.xz | |
Revert 4099 patch that causes an ECC error. Memory has to be written while ECC
error checking is disabled. The purpose of the patch was to preserve memory
used by ACPI resume code. One possible solution is to read that memory and
write it back while ECC error-checking is disabled.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/clear_init_ram.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index 293912175f..ff05f0d439 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -6,7 +6,8 @@ static void __attribute__((noinline)) clear_init_ram(void) // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram - clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ |