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| author | Zheng Bao <fishbaozi@gmail.com> | 2013-02-17 17:27:46 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-18 09:00:24 +0100 |
| commit | ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b (patch) | |
| tree | f0b4cfea96f64f58bbc54c0c3505694f3c90e704 /src/cpu | |
| parent | 178df1121d638650f5eed3210ee94da1981070ea (diff) | |
| download | coreboot-ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b.tar.xz | |
AMD S3: Program the flash in a bigger data packet
According to spi.c in src/southbridge/amd/agesa/hudson
readwrite = (bytesin + readoffby1) << 4 | bytesout;
We can see that Hudson limits the SPI programming data
packet size as 15.
We used to write data to SPI in dword mode. It didn't
take full advantage of the data packet size. We need to
leverage that to speed up programming time.
Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2306
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 56 |
1 files changed, 22 insertions, 34 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ee9d7c9f2d..278c1dadf3 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -178,29 +178,21 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x258); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; msr_data = rdmsr(0x259); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* Disable access to AMD RdDram and WrDram extension bits */ @@ -211,32 +203,24 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM */ msr_data = rdmsr(0xC001001A); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; /* TOM2 */ msr_data = rdmsr(0xC001001D); - flash->write(flash, nvram_pos, 4, &msr_data.lo); - nvram_pos += 4; - flash->write(flash, nvram_pos, 4, &msr_data.hi); - nvram_pos += 4; + flash->write(flash, nvram_pos, 8, &msr_data); + nvram_pos += 8; flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); @@ -290,13 +274,17 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) flash->erase(flash, S3_DATA_VOLATILE_POS, S3_DATA_VOLATILE_SIZE); } +#ifndef SPI_DATA_PACKET_SIZE +#define SPI_DATA_PACKET_SIZE 0xF +#endif nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) { data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); } + flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); |