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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-13 15:21:24 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-16 18:29:28 +0100 |
| commit | f3018f9def40782f9c7dc7baa569eabd027f4c14 (patch) | |
| tree | faf0fb4d20806c22cfa07a4e230d722188ed54cc /src/cpu | |
| parent | 98915bb7a9ab696b3facf9a2fff3525ebb87531f (diff) | |
| download | coreboot-f3018f9def40782f9c7dc7baa569eabd027f4c14.tar.xz | |
Set the fsb timer correctly for Netburst CPUs
On Netburst (Pentium 4) the fsb cannot be read from
MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead.
Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17832
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 60 |
1 files changed, 38 insertions, 22 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 1930ec4539..829f51f2d9 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -47,32 +47,48 @@ static int set_timer_fsb(void) struct cpuinfo_x86 c; int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; + int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 }; get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return -1; - - switch (c.x86_model) { - case 0xe: /* Core Solo/Duo */ - case 0x1c: /* Atom */ - car_set_var(g_timer_fsb, core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); - break; - case 0xf: /* Core 2 or Xeon */ - case 0x17: /* Enhanced Core */ - car_set_var(g_timer_fsb, core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); - break; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ - case 0x3c: /* Haswell BCLK fixed at 100MHz */ - case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - car_set_var(g_timer_fsb, 100); - break; + switch (c.x86) { + case 0x6: + switch (c.x86_model) { + case 0xe: /* Core Solo/Duo */ + case 0x1c: /* Atom */ + car_set_var(g_timer_fsb, + core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); + return 0; + case 0xf: /* Core 2 or Xeon */ + case 0x17: /* Enhanced Core */ + car_set_var(g_timer_fsb, + core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); + return 0; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + car_set_var(g_timer_fsb, 100); + return 0; + default: + car_set_var(g_timer_fsb, 200); + return 0; + } + case 0xf: /* Netburst */ + switch (c.x86_model) { + case 0x2: + car_set_var(g_timer_fsb, + f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]); + return 0; + case 0x3: + case 0x4: + case 0x6: + car_set_var(g_timer_fsb, + core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]); + return 0; + } /* default: fallthrough */ default: - car_set_var(g_timer_fsb, 200); - break; + return -1; } - - return 0; } static inline u32 get_timer_fsb(void) |