binaryPI: Drop non-soc stoneyridge trees

These sources are no longer part of build-tests and transition
to soc/ appears to be completed.

Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

8 files changed, 0 insertions, 417 deletions

diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig
deleted file mode 100644
index 16884f1133..0000000000
--- a/src/cpu/amd/pi/00670F00/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config CPU_AMD_PI_00670F00_FP4
-	bool
-	select X86_AMD_FIXED_MTRRS
-
-config CPU_AMD_PI_00670F00_FT4
-	bool
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
-config HAVE_INIT_TIMER
-	bool
-	default y
-
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0xA1000
-
-endif
diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc
deleted file mode 100644
index 6c6a2b8ac8..0000000000
--- a/src/cpu/amd/pi/00670F00/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += fixme.c
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00670F00/acpi/cpu.asl b/src/cpu/amd/pi/00670F00/acpi/cpu.asl
deleted file mode 100644
index aae3287ba6..0000000000
--- a/src/cpu/amd/pi/00670F00/acpi/cpu.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Processor Object
- *
- */
-Scope (\_PR) {		/* define processor scope */
-	Processor(
-		P000,		/* name space name */
-		0,			/* Unique number for this processor */
-		0x810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-
-	Processor(
-		P001,		/* name space name */
-		1,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P002,		/* name space name */
-		2,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P003,		/* name space name */
-		3,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P004,		/* name space name */
-		4,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P005,		/* name space name */
-		5,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P006,		/* name space name */
-		6,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-	Processor(
-		P007,		/* name space name */
-		7,			/* Unique number for this processor */
-		0x0810,		/* PBLK system I/O address !hardcoded! */
-		0x06		/* PBLKLEN for boot processor */
-		) {
-	}
-} /* End _PR scope */
diff --git a/src/cpu/amd/pi/00670F00/chip_name.c b/src/cpu/amd/pi/00670F00/chip_name.c
deleted file mode 100644
index c5e3b787ad..0000000000
--- a/src/cpu/amd/pi/00670F00/chip_name.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_pi_00670F00_ops = {
-	CHIP_NAME("AMD CPU Family 15h Model 70h-7Fh")
-};
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c
deleted file mode 100644
index e7d7ba5878..0000000000
--- a/src/cpu/amd/pi/00670F00/fixme.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <northbridge/amd/pi/agesawrapper.h>
-#include "amdlib.h"
-
-void amd_initcpuio(void)
-{
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
-	PciData = 1;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* The platform BIOS needs to ensure the memory ranges of SB800
-	 * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
-	 * ACPI) are set to non-posted regions.
-	 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
-	/* last address before processor local APIC at FEE00000 */
-	PciData = 0x00FEDF00;
-	PciData |= 1 << 7;    /* set NP (non-posted) bit */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	/* lowest NP address is HPET at FED00000 */
-	PciData = (0xFED00000 >> 8) | 3;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00FECF00; /* last address before non-posted range */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32)MsrReg;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-	PciData = 0x0000F000;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000003;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
-
-void amd_initmmio(void)
-{
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/*
-	  Set the MMIO Configuration Base Address and Bus Range onto MMIO
-	  configuration base Address MSR register.
-	*/
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \
-		(LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
-
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
-		0x800ull;
-	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
-
-	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
-		LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
-		MsrReg |= 1 << 11;
-		LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
-	}
-}
diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c
deleted file mode 100644
index 5550b9915a..0000000000
--- a/src/cpu/amd/pi/00670F00/model_15_init.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/pae.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
-#include <arch/acpi.h>
-
-#include <amdlib.h>
-#include <PspBaseLib.h>
-
-void PSPProgBar3Msr(void *Buffer);
-
-void PSPProgBar3Msr(void *Buffer)
-{
-	u32 Bar3Addr;
-	u64 Tmp64;
-	/* Get Bar3 Addr */
-	Bar3Addr = PspLibPciReadPspConfig(0x20);
-	Tmp64 = Bar3Addr;
-	printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
-	LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
-	LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
-}
-
-static void model_15_init(device_t dev)
-{
-	printk(BIOS_DEBUG, "Model 15 Init.\n");
-
-	u8 i;
-	msr_t msr;
-	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	u32 siblings;
-#endif
-
-	disable_cache();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	// BSP: make a0000-bffff UC, c0000-fffff WB
-	msr.lo = msr.hi = 0;
-	wrmsr(0x259, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	wrmsr(0x250, msr);
-	wrmsr(0x258, msr);
-	for (msrno = 0x268; msrno <= 0x26f; msrno++)
-		wrmsr(msrno, msr);
-
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	x86_mtrr_check();
-	x86_enable_cache();
-
-	/* zero the machine check error status registers */
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < 6; i++)
-		wrmsr(MCI_STATUS + (i * 4), msr);
-
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-	PSPProgBar3Msr(NULL);
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-
-	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_15_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x670f00 },
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 91363c5f59..c0e942837e 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -17,8 +17,6 @@ config CPU_AMD_PI
 	bool
 	default y if CPU_AMD_PI_00630F01
 	default y if CPU_AMD_PI_00730F01
-	default y if CPU_AMD_PI_00670F00_FP4
-	default y if CPU_AMD_PI_00670F00_FT4
 	default y if CPU_AMD_PI_00660F01
 	default n
 	select ARCH_BOOTBLOCK_X86_32
@@ -71,5 +69,4 @@ endif # CPU_AMD_PI
 
 source src/cpu/amd/pi/00630F01/Kconfig
 source src/cpu/amd/pi/00730F01/Kconfig
-source src/cpu/amd/pi/00670F00/Kconfig
 source src/cpu/amd/pi/00660F01/Kconfig
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index a5ed12054a..3b3f7accc9 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -15,8 +15,6 @@
 
 subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
-subdirs-$(CONFIG_CPU_AMD_PI_00670F00_FP4) += 00670F00
-subdirs-$(CONFIG_CPU_AMD_PI_00670F00_FT4) += 00670F00
 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
 ramstage-$(CONFIG_SPI_FLASH) += spi.c