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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-11-03 15:02:15 +0000
committerStefan Reinauer <stepan@openbios.org>2009-11-03 15:02:15 +0000
commitc6680487b950e79164db8ad340648e87adc27d91 (patch)
treef861a380cb943e4435b2f194b6b477b4a6560df3 /src/cpu
parent7110d40fbf27b1fafe70e3cd560f53ca7be094a5 (diff)
downloadcoreboot-c6680487b950e79164db8ad340648e87adc27d91.tar.xz
Some fixes.
Atom does not like 36bit MTRRs in CAR setup. Enable XIP setup again (works with 32bit MTRRs) Keep code more similar to 6ex code.. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc15
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_post.c4
2 files changed, 11 insertions, 8 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 92cf92f0f0..a216aa3295 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -103,7 +103,6 @@ clear_mtrrs:
//movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
-#endif
post_code(0x29)
/* Enable Cache As RAM mode by disabling cache */
@@ -111,29 +110,33 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
-#if 0
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
- /* Enable cache for our code in Flash because we do CONFIG_XIP here */
+ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $0x0000000f, %edx
+ movl $0x00000000, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
-#endif
post_code(0x2a)
/* enable cache */
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
- movl %eax, %cr0
+ movl %eax, %cr0
+#endif
/* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+ /* leave some space for the struct ehci_debug_info */
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
movl %eax, %esp
/* Restore the BIST result */
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_post.c b/src/cpu/intel/model_106cx/cache_as_ram_post.c
index f5f4ff856e..09446fdea1 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_post.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_post.c
@@ -60,7 +60,7 @@
"wrmsr\n"
"movl $MTRRphysMask_MSR(0), %ecx\n"
"movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
- "movl $0x0000000f, %edx\n" // 36bit address space
+ "movl $0x00000000, %edx\n"
"wrmsr\n"
"movb $0x35, %al\noutb %al, $0x80\n"
#endif
@@ -97,7 +97,7 @@
"wrmsr\n"
"movl $MTRRphysMask_MSR(0), %ecx\n"
"movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
- "movl $0x0000000f, %edx\n" // 36bit address space
+ "movl $0x00000000, %edx\n"
"wrmsr\n"
"movb $0x39, %al\noutb %al, $0x80\n"