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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-20 12:47:52 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-03-04 06:15:55 +0100 |
| commit | ead8751367867b798cea0709628c8eda780f20c8 (patch) | |
| tree | da36e56d8b0b8388acaddb9f6a945b0361bcd202 /src/cpu | |
| parent | 29c1afce629efe2e758d47707d6c2d6930b3c266 (diff) | |
| download | coreboot-ead8751367867b798cea0709628c8eda780f20c8.tar.xz | |
cpu/amd/model_10xxx: Refactor model detection to reduce code duplication
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.
Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_10xxx/powernow_acpi.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c index 0b3681cbb1..feb8f01f60 100644 --- a/src/cpu/amd/model_10xxx/powernow_acpi.c +++ b/src/cpu/amd/model_10xxx/powernow_acpi.c @@ -31,6 +31,8 @@ #include <cpu/amd/amdfam10_sysconf.h> #include <arch/cpu.h> #include <northbridge/amd/amdht/AsPsDefs.h> +#include <northbridge/amd/amdmct/mct/mct.h> +#include <northbridge/amd/amdmct/amddefs.h> static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power, u32 *pstate_latency, u32 *pstate_control, @@ -114,8 +116,6 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) printk(BIOS_INFO, "processor_brand=%s\n", processor_brand); uint32_t dtemp; - uint32_t cpuid_fms; - uint8_t model; uint8_t node_count; /* @@ -124,13 +124,10 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore */ printk(BIOS_INFO, "Pstates algorithm ...\n"); - /* Get CPU model */ - cpuid_fms = cpuid_eax(0x80000001); - model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4); /* Get number of cores */ dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8); cmp_cap = (dtemp & 0x3000) >> 12; - if ((model == 0x8) || (model == 0x9)) /* revision D */ + if (mctGetLogicalCPUID(0) & AMD_FAM10_REV_D) /* revision D */ cmp_cap |= (dtemp & 0x8000) >> 13; /* Get number of nodes */ dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60); |