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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 10:00:28 +0300
committerMartin Roth <martinroth@google.com>2016-06-21 00:49:12 +0200
commit15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch)
tree99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/cpu
parent4c3de9c3edd7cb6fabc72337171862930354f0bf (diff)
downloadcoreboot-15fa992cc8467b4cbd8ebea62e3e4c947827137e.tar.xz
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc10
-rw-r--r--src/cpu/intel/socket_BGA956/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_LGA771/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_LGA775/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_mFCPGA478/Makefile.inc1
5 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 2eb824cea7..f4c4af86d3 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -132,7 +132,12 @@ clear_mtrrs:
post_code(0x23)
/* Call romstage.c main function. */
- call main
+ call romstage_main
+
+ /* Save return value from romstage_main. It contains the stack to use
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
+ movl %eax, %ebx
post_code(0x2f)
@@ -219,7 +224,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
- movl $CONFIG_RAMTOP, %esp
+ /* Setup stack as indicated by return value from romstage_main(). */
+ movl %ebx, %esp
movl %esp, %ebp
call copy_and_run
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 2325bb9e32..22c1a7c9eb 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -10,3 +10,4 @@ subdirs-y += ../speedstep
# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
index 8235fc52aa..d0a5b63264 100644
--- a/src/cpu/intel/socket_LGA771/Makefile.inc
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -9,3 +9,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index 54a762eb44..371a801425 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -16,3 +16,4 @@ subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index 749f6abf06..6056d3c453 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -12,3 +12,4 @@ subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c