summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2016-03-15 09:05:54 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-16 18:55:51 +0100
commit264bf0b27e6202dfca27c285c9dde10d08b8f023 (patch)
tree6ce70301f75bfaff39e95b2b17130aa9935a4d02 /src/cpu
parent94534b31328311e3a3488a7f8201bc0abab9fb1d (diff)
downloadcoreboot-264bf0b27e6202dfca27c285c9dde10d08b8f023.tar.xz
cpu/x86/mtrr: move cache_ramstage() to its only user
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 2e31a6e113..3d7ad11720 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -20,14 +20,6 @@ void set_var_mtrr(
}
#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
-static void cache_ramstage(void)
-{
- /* Enable caching for lower 1MB and ram stage using variable mtrr */
- disable_cache();
- set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
- enable_cache();
-}
-
const int addr_det = 0;
/* the fixed and variable MTRRs are power-up with random values,