diff options
author | Patrick Georgi <pgeorgi@chromium.org> | 2015-05-05 22:27:25 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-05-05 22:49:18 +0200 |
commit | 26e24cc12de487c8fe350925147cb3442b49c240 (patch) | |
tree | b8b28556d6917d5cd6ae5fee1cd5991252f478d0 /src/cpu | |
parent | f4f028790a492120ce9e7b3292a17664a8c7613d (diff) | |
download | coreboot-26e24cc12de487c8fe350925147cb3442b49c240.tar.xz |
3rdparty: move to 3rdparty/blobs
There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
23 files changed, 24 insertions, 24 deletions
diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index 074aeda167..be9e1bef88 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage -vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository) +vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository) diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 6d1fd0fc4d..6001cc75b6 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -37,7 +37,7 @@ config GEODE_VSA_FILE config VSA_FILENAME string "AMD Geode LX VSA path and filename" depends on GEODE_VSA_FILE - default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" + default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" help The path and filename of the file to use as VSA. diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index ffa0688d67..9edb332b4b 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage -vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository) +vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository) diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c index 3338cc49b2..31bb14bae8 100644 --- a/src/cpu/intel/haswell/microcode_blob.c +++ b/src/cpu/intel/haswell/microcode_blob.c @@ -23,8 +23,8 @@ unsigned microcode[] = { * a very good reason why we only use one at a time? */ #if CONFIG_INTEL_LYNXPOINT_LP - #include "../../../../blobs/cpu/intel/model_4065x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h" #else - #include "../../../../blobs/cpu/intel/model_306cx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h" #endif }; diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c index c98d5ff298..88e95db1d8 100644 --- a/src/cpu/intel/model_1067x/microcode_blob.c +++ b/src/cpu/intel/model_1067x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_1067ax[] = { - #include "../../../../blobs/cpu/intel/model_1067x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h" }; diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c index 94ea96d18d..5a0257ab91 100644 --- a/src/cpu/intel/model_106cx/microcode_blob.c +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_106cx[] = { - #include "../../../../blobs/cpu/intel/model_106cx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h" }; diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c index 35c5c98952..53b21b449e 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.c +++ b/src/cpu/intel/model_2065x/microcode_blob.c @@ -18,5 +18,5 @@ */ unsigned microcode[] = { - #include "../../../../blobs/cpu/intel/model_2065x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h" }; diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c index dc1c2bd50d..5d725ffde5 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.c +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -18,5 +18,5 @@ */ unsigned microcode[] = { - #include "../../../../blobs/cpu/intel/model_206ax/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h" }; diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c index fcddd617b1..85117085b7 100644 --- a/src/cpu/intel/model_65x/microcode_blob.c +++ b/src/cpu/intel/model_65x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_65x[] = { - #include "../../../../blobs/cpu/intel/model_65x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h" }; diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c index 5c07456207..672dee3282 100644 --- a/src/cpu/intel/model_67x/microcode_blob.c +++ b/src/cpu/intel/model_67x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_67x[] = { - #include "../../../../blobs/cpu/intel/model_67x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h" }; diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c index 7246527b2a..db32f3478f 100644 --- a/src/cpu/intel/model_68x/microcode_blob.c +++ b/src/cpu/intel/model_68x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_68x[] = { - #include "../../../../blobs/cpu/intel/model_68x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h" }; diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c index 37e19f3c1f..04bc717809 100644 --- a/src/cpu/intel/model_69x/microcode_blob.c +++ b/src/cpu/intel/model_69x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_69x[] = { - #include "../../../../blobs/cpu/intel/model_69x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h" }; diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c index cf5a95a47f..dbfab5daa0 100644 --- a/src/cpu/intel/model_6bx/microcode_blob.c +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6bx[] = { - #include "../../../../blobs/cpu/intel/model_6bx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h" }; diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c index 4871c7c80d..50e15cc311 100644 --- a/src/cpu/intel/model_6dx/microcode_blob.c +++ b/src/cpu/intel/model_6dx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6dx[] = { - #include "../../../../blobs/cpu/intel/model_6dx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h" }; diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c index 2068a1dc69..2c749a7661 100644 --- a/src/cpu/intel/model_6ex/microcode_blob.c +++ b/src/cpu/intel/model_6ex/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6ex[] = { - #include "../../../../blobs/cpu/intel/model_6ex/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h" }; diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c index 371f9760ee..8044e51ac7 100644 --- a/src/cpu/intel/model_6fx/microcode_blob.c +++ b/src/cpu/intel/model_6fx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6fx[] = { - #include "../../../../blobs/cpu/intel/model_6fx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h" }; diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c index 489de4b81f..463faf0275 100644 --- a/src/cpu/intel/model_6xx/microcode_blob.c +++ b/src/cpu/intel/model_6xx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6xx[] = { - #include "../../../../blobs/cpu/intel/model_6xx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h" }; diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c index 32ca360ea0..7cef6d1022 100644 --- a/src/cpu/intel/model_f0x/microcode_blob.c +++ b/src/cpu/intel/model_f0x/microcode_blob.c @@ -1,4 +1,4 @@ /* 256KB cache */ unsigned microcode_updates_f0x[] = { - #include "../../../../blobs/cpu/intel/model_f0x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h" }; diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c index 63af4a3567..a9b25d7fb0 100644 --- a/src/cpu/intel/model_f1x/microcode_blob.c +++ b/src/cpu/intel/model_f1x/microcode_blob.c @@ -1,4 +1,4 @@ /* 256KB cache */ unsigned microcode_updates_f1x[] = { - #include "../../../../blobs/cpu/intel/model_f1x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h" }; diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c index 6a5eee7bf9..3815f060b6 100644 --- a/src/cpu/intel/model_f2x/microcode_blob.c +++ b/src/cpu/intel/model_f2x/microcode_blob.c @@ -1,4 +1,4 @@ /* 512KB cache */ unsigned microcode_updates_f2x[] = { - #include "../../../../blobs/cpu/intel/model_f2x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h" }; diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c index d93912f933..fb46747330 100644 --- a/src/cpu/intel/model_f3x/microcode_blob.c +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_f3x[] = { - #include "../../../../blobs/cpu/intel/model_f3x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h" }; diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c index 3ec4479674..b061dcc375 100644 --- a/src/cpu/intel/model_f4x/microcode_blob.c +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_f4x[] = { - #include "../../../../blobs/cpu/intel/model_f4x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h" }; diff --git a/src/cpu/samsung/exynos5250/update-bl1.sh b/src/cpu/samsung/exynos5250/update-bl1.sh index 755239992a..7fede4c778 100644 --- a/src/cpu/samsung/exynos5250/update-bl1.sh +++ b/src/cpu/samsung/exynos5250/update-bl1.sh @@ -1,7 +1,7 @@ #!/bin/sh BL1_NAME="E5250.nbl1.bin" -BL1_PATH="blobs/cpu/samsung/exynos5250/" +BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/" BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2" get_bl1() { |