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authorNico Huber <nico.h@gmx.de>2019-02-10 19:35:41 +0100
committerNico Huber <nico.h@gmx.de>2019-02-12 13:34:16 +0000
commit4c7eee27447e1a41808a11be8ce55031e97fdccf (patch)
treea307d6c4aeaf26d210bcd23b15c01c8cd8493250 /src/cpu
parent4dba4975b4e9710e159a000f7afed46a306134b3 (diff)
downloadcoreboot-4c7eee27447e1a41808a11be8ce55031e97fdccf.tar.xz
postcar: Make more use of postcar_frame_add_romcache()
Some similar calls to postcar_frame_add_mtrr() were added in the meantime or were under review while postcar_frame_add_romcache() was introduced. Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ff729d6285..cfc4a13dd3 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -55,8 +55,7 @@ void platform_enter_postcar(void)
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);