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authorVadim Bendebury <vbendeb@chromium.org>2012-06-19 12:56:57 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-07-24 22:15:19 +0200
commit537b4e09e644107ed644cd88f8a7fd488406b9a2 (patch)
tree92b1fc622e2f89c55149064396459ac362f2be17 /src/cpu
parentef6b08cc486e5d97103211dfeb3d629552a92e43 (diff)
downloadcoreboot-537b4e09e644107ed644cd88f8a7fd488406b9a2.tar.xz
Add code to read Intel microcode from CBFS
When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in CBFS and pass it to intel_update_microcode() instead of using the compiled in array. CBFS accesses in pre-RAM and 'normal' environments are provided through different API. Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1296 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/microcode/microcode.c30
-rw-r--r--src/cpu/intel/model_206ax/bootblock.c6
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c7
3 files changed, 42 insertions, 1 deletions
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index ec42fb91d7..af83faf69d 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2000 Ronald G. Minnich
*
* This program is free software; you can redistribute it and/or modify
@@ -27,6 +28,14 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
+#if CONFIG_MICROCODE_IN_CBFS
+#ifdef __PRE_RAM__
+#include <arch/cbfs.h>
+#else
+#include <cbfs.h>
+#endif
+#endif
+
struct microcode {
u32 hdrver; /* Header Version */
u32 rev; /* Update Revision */
@@ -68,6 +77,9 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
+#if CONFIG_MICROCODE_IN_CBFS
+static
+#endif
void intel_update_microcode(const void *microcode_updates)
{
u32 eax;
@@ -131,3 +143,21 @@ void intel_update_microcode(const void *microcode_updates)
}
}
}
+
+#if CONFIG_MICROCODE_IN_CBFS
+
+#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+
+void intel_update_microcode_from_cbfs(void)
+{
+ void *microcode_blob;
+
+#ifdef __PRE_RAM__
+ microcode_blob = walkcbfs((char *) MICROCODE_CBFS_FILE);
+#else
+ microcode_blob = cbfs_find_file(MICROCODE_CBFS_FILE,
+ CBFS_TYPE_MICROCODE);
+#endif
+ intel_update_microcode(microcode_blob);
+}
+#endif
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 62d9b4edeb..4061bb7b5a 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -23,9 +23,11 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
+#if !CONFIG_MICROCODE_IN_CBFS
static const uint32_t microcode_updates[] = {
#include "microcode_blob.h"
};
+#endif
#include <cpu/intel/microcode/microcode.c>
@@ -61,5 +63,9 @@ static void enable_rom_caching(void)
static void bootblock_cpu_init(void)
{
enable_rom_caching();
+#if CONFIG_MICROCODE_IN_CBFS
+ intel_update_microcode_from_cbfs();
+#else
intel_update_microcode(microcode_updates);
+#endif
}
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index dda7d354b7..87bc585d86 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -115,9 +115,11 @@ static acpi_cstate_t cstate_map[] = {
{ 0 }
};
+#if !CONFIG_MICROCODE_IN_CBFS
static const uint32_t microcode_updates[] = {
#include "microcode_blob.h"
};
+#endif
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
@@ -387,8 +389,11 @@ static void model_206ax_init(device_t cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Update the microcode */
+#if CONFIG_MICROCODE_IN_CBFS
+ intel_update_microcode_from_cbfs();
+#else
intel_update_microcode(microcode_updates);
+#endif
/* Clear out pending MCEs */
configure_mca();