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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-06-27 06:10:38 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-01 04:18:41 +0000
commit6bdaaefb3077938b86a65725a7732c992a0b2328 (patch)
tree3022f9e85948e0cb6331c69add42c2492457d208 /src/cpu
parent86dbe0f3072d87830b073bd4f372961f924e6df0 (diff)
downloadcoreboot-6bdaaefb3077938b86a65725a7732c992a0b2328.tar.xz
intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHz
Prior to commit d731a24 src/cpu/intel: Set get_ia32_fsb function common value of 200 was silently used as a default for fsp_rangeley (model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb(). After the commit, get_ia32_fsb() returns -2, eventually resulting with divide-by-zero in timer_monotonic_get(), as get_timer_fsb() returns 0. Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix, using BCLK = 100 MHz based on the comments in northbridge/intel/fsp_rangeley/udelay.c Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/common/fsb.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 83220de3bc..d66e87a396 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -46,6 +46,7 @@ static int get_fsb(void)
case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+ case 0x4d: /* Rangeley BCLK fixed at 100MHz */
ret = 100;
break;
}