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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-20 13:31:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 05:39:03 +0200
commit9ec691429f1d851c08297d65ff56729fccc6397c (patch)
tree5ed1c21ff1b368162444b7c6001c8cc73d438f88 /src/cpu
parenta27fba67a0dc8f2d2b991b08dbcd2eb485baa8d7 (diff)
downloadcoreboot-9ec691429f1d851c08297d65ff56729fccc6397c.tar.xz
intel car: Remove guard on XIP_ROM_SIZE
These guards have been removed starting with model_206ax. Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15758 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc3
-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc2
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc2
3 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 3d7be8bf5e..442c2b4a33 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -225,8 +225,6 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
-#if CONFIG_XIP_ROM_SIZE
-
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@@ -246,7 +244,6 @@ clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 095b9b6cda..84a55c738a 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -302,7 +302,6 @@ no_msr_11e:
post_code(0x2d)
-#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
@@ -319,7 +318,6 @@ no_msr_11e:
rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 6b80e7ae7b..edd9e6c961 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -96,7 +96,6 @@ clear_mtrrs:
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
-#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
@@ -113,7 +112,6 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax