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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-17 10:56:26 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 15:52:09 +0000
commita342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch)
tree4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/cpu
parent9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff)
downloadcoreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/family_10h-family_15h/fidvid.c2
-rw-r--r--src/cpu/amd/family_10h-family_15h/powernow_acpi.c2
-rw-r--r--src/cpu/amd/microcode/microcode.c2
-rw-r--r--src/cpu/via/nano/nano_init.c10
-rw-r--r--src/cpu/via/nano/update_ucode.c8
5 files changed, 12 insertions, 12 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 91b9ad7560..428924df34 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -682,7 +682,7 @@ static void waitCurrentPstate(u32 target_pstate) {
do { // should we just go on instead ?
pstate_msr = rdmsr(PS_STS_REG);
- } while ( pstate_msr.lo != target_pstate );
+ } while (pstate_msr.lo != target_pstate);
}
}
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
index 61da88cc49..d228858a8e 100644
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
@@ -226,7 +226,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
fam10h_rev_e = 1;
/*
- * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
+ * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
*/
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 541d5a81aa..68b6953be8 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -129,7 +129,7 @@ static void apply_microcode_patch(const struct microcode *m)
msr = rdmsr(0x8b);
new_patch_id = msr.lo;
- UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
+ UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,
(new_patch_id == m->patch_id) ? "success" : "fail");
}
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index 985a3c7303..cbd80cee72 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -71,7 +71,7 @@ static void nano_set_max_fid_vid(void)
printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
cur_vid, min_vid, max_vid);
- if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
+ if ((cur_fid != max_fid) || (cur_vid != max_vid)) {
/* Set highest frequency and VID */
msr.lo = msr.hi;
msr.hi = 0;
@@ -101,7 +101,7 @@ static void nano_power(void)
* This MSR is not documented by VIA docs, other than setting these
* bits */
msr = rdmsr(NANO_MYSTERIOUS_MSR);
- msr.lo |= ( (1 << 7) | (1 << 4) );
+ msr.lo |= ((1 << 7) | (1 << 4));
/* FIXME: Do we have a 6-bit or 7-bit VRM?
* set bit [5] for 7-bit, or don't set it for 6 bit VRM
* This will probably require a Kconfig option
@@ -114,15 +114,15 @@ static void nano_power(void)
/* Enable TM3 */
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= ( (1 << 3) | (1 << 13) );
+ msr.lo |= ((1 << 3) | (1 << 13));
wrmsr(IA32_MISC_ENABLE, msr);
- u8 stepping = ( cpuid_eax(0x1) ) &0xf;
+ u8 stepping = (cpuid_eax(0x1)) & 0xf;
if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
+ msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.hi |= (1 << 0); /* C4e */
wrmsr(IA32_MISC_ENABLE, msr);
}
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
index b8bfd7da5a..efabac6224 100644
--- a/src/cpu/via/nano/update_ucode.c
+++ b/src/cpu/via/nano/update_ucode.c
@@ -43,9 +43,9 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
static void nano_print_ucode_info(const nano_ucode_header *ucode)
{
printk(BIOS_SPEW, "Microcode update information:\n");
- printk(BIOS_SPEW, "Name: %8s\n", ucode->name );
+ printk(BIOS_SPEW, "Name: %8s\n", ucode->name);
printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
- ucode->day, ucode->year );
+ ucode->day, ucode->year);
}
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
@@ -54,7 +54,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
if (ucode->signature != NANO_UCODE_SIGNATURE)
return NANO_UCODE_SIGNATURE_ERROR;
/* The size of the head must be exactly 12 double words */
- if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
return NANO_UCODE_WRONG_SIZE;
/* How about a checksum ? Checksum must be 0
@@ -119,7 +119,7 @@ unsigned int nano_update_ucode(void)
/* We might do a lot of loops searching for the microcode updates, but
* keep in mind, nano_ucode_is_valid searches for the signature before
* doing anything else. */
- for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
+ for (i = 0; i < (ucode_len >> 2); /* don't increment i here */)
{
ucode_update_status stat;
const nano_ucode_header * ucode = (void *)(&ucode_data[i]);