diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-12 10:36:47 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 04:40:32 +0000 |
| commit | a347630641f796a39311cb0ddc6c9217e56eab07 (patch) | |
| tree | e37d26468c165ebb1b2d11721aed11d6ab9164e4 /src/cpu | |
| parent | 4913d8aed05d838d5be9c144f7716968ce2962c9 (diff) | |
| download | coreboot-a347630641f796a39311cb0ddc6c9217e56eab07.tar.xz | |
intel/smm/gen1: Split alternative SMRR register function
The non-alternative one will have inlined version available
with the new header.
Change-Id: I208ac84fdf5d8041a1901cc2331769cd3a8d6bea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/smm/gen1/smmrelocate.c | 44 |
1 files changed, 27 insertions, 17 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index fd98c3057c..f196706a36 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -78,27 +78,32 @@ bool cpu_has_alternative_smrr(void) } } +static void write_smrr_alt(struct smm_relocation_params *relo_params) +{ + msr_t msr; + msr = rdmsr(IA32_FEATURE_CONTROL); + /* SMRR enabled and feature locked */ + if (!((msr.lo & SMRR_ENABLE) + && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { + printk(BIOS_WARNING, + "SMRR not enabled, skip writing SMRR...\n"); + return; + } + + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + + wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + static void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - if (cpu_has_alternative_smrr()) { - msr_t msr; - msr = rdmsr(IA32_FEATURE_CONTROL); - /* SMRR enabled and feature locked */ - if (!((msr.lo & SMRR_ENABLE) - && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { - printk(BIOS_WARNING, - "SMRR not enabled, skip writing SMRR...\n"); - return; - } - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); - } else { - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - } + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) @@ -235,7 +240,12 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) + if (!(mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)) + return; + + if (cpu_has_alternative_smrr()) + write_smrr_alt(relo_params); + else write_smrr(relo_params); } |