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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-21 06:59:30 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-22 10:48:18 +0200
commitb4f827d45a08d849df9d15abd644e3a98a6f1932 (patch)
tree068faec60a03a6b311d2cae0d2d6398cf82b0b8e /src/cpu
parente00b2de71cc234a9d043125539d503bbaf08aa26 (diff)
downloadcoreboot-b4f827d45a08d849df9d15abd644e3a98a6f1932.tar.xz
intel cache-as-ram: Fix comment about MTRRs
Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15282 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc4
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 349ec05f03..3d7be8bf5e 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -321,8 +321,8 @@ lout:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
+ * after cache-as-ram is torn down.
+ */
movl %eax, %ebx
/* We don't need CAR from now on. */
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index f5256adb76..1e21d9dc6d 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -342,8 +342,8 @@ no_msr_11e:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
+ * after cache-as-ram is torn down.
+ */
movl %eax, %ebx
post_code(0x30)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index f4c4af86d3..79383e163f 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -135,8 +135,8 @@ clear_mtrrs:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
+ * after cache-as-ram is torn down.
+ */
movl %eax, %ebx
post_code(0x2f)