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authorAaron Durbin <adurbin@chromium.org>2013-04-29 16:57:10 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-05-01 07:14:36 +0200
commitc46cc6f149c42653344d6e9f3656a4212fc46cef (patch)
tree785ff1c5861ac336546f6c1ba98e5997edf0e222 /src/cpu
parenta421791db815fb2e2da9b1ce4bec78c97665b62f (diff)
downloadcoreboot-c46cc6f149c42653344d6e9f3656a4212fc46cef.tar.xz
haswell: 24MHz monotonic time implementation
Haswell ULT devices have a 24MHz package-level counter. Use this counter to provide a timer_monotonic_get() implementation. Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3153 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/Kconfig7
-rw-r--r--src/cpu/intel/haswell/Makefile.inc1
-rw-r--r--src/cpu/intel/haswell/monotonic_timer.c62
3 files changed, 70 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 5f27d4c7e1..13861f9185 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -54,4 +54,11 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
the system will reset otherwise the ramstage will be reloaded from
cbfs.
+config MONOTONIC_TIMER_MSR
+ def_bool n
+ depends on INTEL_LYNXPOINT_LP
+ select HAVE_MONOTONIC_TIMER
+ help
+ Provide a monotonic timer using the 24MHz MSR counter.
+
endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a19a8c5270..90ffd66699 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -5,6 +5,7 @@ romstage-y += romstage.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
+ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/haswell/monotonic_timer.c b/src/cpu/intel/haswell/monotonic_timer.c
new file mode 100644
index 0000000000..c51bcbd0c9
--- /dev/null
+++ b/src/cpu/intel/haswell/monotonic_timer.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <timer.h>
+
+#define MSR_COUNTER_24_MHz 0x637
+static struct monotonic_counter {
+ int initialized;
+ struct mono_time time;
+ uint32_t last_value;
+} mono_counter;
+
+static inline uint32_t read_counter_msr(void)
+{
+ /* Even though the MSR is 64-bit it is assumed that the hardware
+ * is polled frequently enough to only use the lower 32-bits. */
+ msr_t counter_msr;
+
+ counter_msr = rdmsr(MSR_COUNTER_24_MHz);
+
+ return counter_msr.lo;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ uint32_t current_tick;
+ uint32_t usecs_elapsed;
+
+ if (!mono_counter.initialized) {
+ mono_counter.last_value = read_counter_msr();
+ mono_counter.initialized = 1;
+ }
+
+ current_tick = read_counter_msr();
+ usecs_elapsed = (current_tick - mono_counter.last_value) / 24;
+
+ /* Update current time and tick values only if a full tick occurred. */
+ if (usecs_elapsed) {
+ mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+ mono_counter.last_value = current_tick;
+ }
+
+ /* Save result. */
+ *mt = mono_counter.time;
+}