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| author | Martin Roth <martin@coreboot.org> | 2020-06-03 19:24:11 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-23 21:28:40 +0000 |
| commit | cfc170b2133c9e6b385d218bdc5677da29275264 (patch) | |
| tree | dedc2fd38d4057c7996d15a048dfe6d819dfdeed /src/cpu | |
| parent | f3343f2560e23d2eb1ce7d9fbb9eb75b9498825c (diff) | |
| download | coreboot-cfc170b2133c9e6b385d218bdc5677da29275264.tar.xz | |
src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/lapic/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/cpu/x86/pae/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/x86/tsc/Makefile.inc | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 0d114782e1..ea160148cf 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -6,7 +6,7 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c -verstage-y += boot_cpu.c +verstage_x86-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d41b..3f33e31379 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,7 +2,7 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c -verstage-y += earlymtrr.c +verstage_x86-y += earlymtrr.c bootblock-y += debug.c romstage-y += debug.c @@ -10,4 +10,4 @@ postcar-y += debug.c ramstage-y += debug.c bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +verstage_x86-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 62176d20b8..70e0b2ffde 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,5 +1,5 @@ bootblock-y += pgtbl.c -verstage-y += pgtbl.c +verstage_x86-y += pgtbl.c romstage-y += pgtbl.c postcar-y += pgtbl.c ramstage-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5051..a0cd145c51 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c |