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authorArthur Heymans <arthur@aheymans.xyz>2019-11-09 06:50:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:25:42 +0000
commitdf9cdcfc383ac38c2238fd6d640c9260028906f7 (patch)
treec72389e5b014119ecc632dc279c6c7162acc433a /src/cpu
parentfee2fdecc2b6c260fcb6caf3348ee948a83cdbd7 (diff)
downloadcoreboot-df9cdcfc383ac38c2238fd6d640c9260028906f7.tar.xz
arch/x86/car.ld: Rename suffix _start/_end
This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/romstage.c2
-rw-r--r--src/cpu/qemu-x86/cache_as_ram_bootblock.S2
6 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index a1bec12ede..0e0fa77bb0 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -173,7 +173,7 @@ addrsize_set_high:
movl %eax, %cr0
/* Setup the stack. */
- mov $_car_stack_end, %esp
+ mov $_ecar_stack, %esp
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 08ad195964..cd6972062c 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -215,7 +215,7 @@ end_microcode_update:
movl %eax, %cr0
/* Setup the stack. */
- mov $_car_stack_end, %esp
+ mov $_ecar_stack, %esp
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 33f0bfd2a3..a3487dbe34 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -161,7 +161,7 @@ addrsize_set_high:
movl %eax, %cr0
/* Setup the stack. */
- mov $_car_stack_end, %esp
+ mov $_ecar_stack, %esp
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 58e411dcc3..7815eb3235 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -376,7 +376,7 @@ fill_cache:
rep stosl
/* Setup the stack. */
- mov $_car_stack_end, %esp
+ mov $_ecar_stack, %esp
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 547b1211df..1525233e39 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -46,7 +46,7 @@ static void romstage_main(unsigned long bist)
printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n",
size);
- stack_base = (u32 *) (_car_stack_end - size);
+ stack_base = (u32 *) (_ecar_stack - size);
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index f5678a1807..1fa0018dc8 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -34,7 +34,7 @@ cache_as_ram:
post_code(0x21)
- movl $_car_stack_end, %esp
+ movl $_ecar_stack, %esp
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp