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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 23:34:13 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 16:45:48 +0000
commite27c013f39f0433dac57a754b3484553a536f30d (patch)
tree6e9b9d20964ac994c453079ca9c13cb145480dbd /src/cpu
parentdc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (diff)
downloadcoreboot-e27c013f39f0433dac57a754b3484553a536f30d.tar.xz
nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK
Console init in bootblock will be done in a separate CL. Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S8
-rw-r--r--src/cpu/intel/socket_441/Kconfig9
-rw-r--r--src/cpu/intel/socket_441/Makefile.inc3
-rw-r--r--src/cpu/intel/socket_m/Kconfig8
-rw-r--r--src/cpu/intel/socket_m/Makefile.inc3
6 files changed, 21 insertions, 14 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 0e0fa77bb0..73618d92f6 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
.global bootblock_pre_c_entry
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 7815eb3235..fdeb0af8ec 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -18,22 +18,14 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
-/* Fixed location, ASSERTED in failover.ld if it changes. */
-.set ap_sipi_vector_in_rom, 0xff
-#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
.global bootblock_pre_c_entry
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index ac249c5755..af43f72e53 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -8,6 +8,11 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_106CX
select MMX
select SSE
+ select SETUP_XIP_CACHE
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x4000
config DCACHE_RAM_BASE
hex
@@ -17,4 +22,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
endif # CPU_INTEL_SOCKET_441
diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
index 7993294a17..e21bf03ff5 100644
--- a/src/cpu/intel/socket_441/Makefile.inc
+++ b/src/cpu/intel/socket_441/Makefile.inc
@@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
index 02330f9cb8..8b1f5edda5 100644
--- a/src/cpu/intel/socket_m/Kconfig
+++ b/src/cpu/intel/socket_m/Kconfig
@@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x8000
+
endif
diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
index 96f16dc6b3..61e4e58f13 100644
--- a/src/cpu/intel/socket_m/Makefile.inc
+++ b/src/cpu/intel/socket_m/Makefile.inc
@@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+bootblock-y += ../car/core2/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c