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authorAaron Durbin <adurbin@chromium.org>2013-03-29 16:23:23 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-04-01 23:29:11 +0200
commitebf142a12ce4911b766bd618483434519efba0d5 (patch)
treefc41e294b862e6527da7714ac0e99a9709705549 /src/cpu
parentb39ba2efcfb0da48c8e7719d1c8db037b567a8bc (diff)
downloadcoreboot-ebf142a12ce4911b766bd618483434519efba0d5.tar.xz
boot: add disable_cache_rom() function
On certain architectures such as x86 the bootstrap processor does most of the work. When CACHE_ROM is employed it's appropriate to ensure that the caching enablement of the ROM is disabled so that the caching settings are symmetric before booting the payload or OS. Tested this on an x86 machine that turned on ROM caching. Linux did not complain about asymmetric MTRR settings nor did the ROM show up as cached in the MTRR settings. Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/mtrr/mtrr.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 253a7c318b..608912754c 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -29,6 +29,7 @@
#include <string.h>
#include <console/console.h>
#include <device/device.h>
+#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
@@ -406,6 +407,11 @@ void x86_mtrr_disable_rom_caching(void)
wrmsr(MTRRphysBase_MSR(index), msr_val);
enable_cache();
}
+
+void disable_cache_rom(void)
+{
+ x86_mtrr_disable_rom_caching();
+}
#endif
struct var_mtrr_state {