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authorAaron Durbin <adurbin@chromium.org>2016-05-05 10:34:22 -0500
committerAaron Durbin <adurbin@chromium.org>2016-05-06 16:49:37 +0200
commitef1052918775d321928410aebedeb21ac96b36c0 (patch)
tree663f875ea2890eb2b930888d2a44fa77b88f90a9 /src/cpu
parentab00d779ed323c1b58af687c1e2ad78536d3822f (diff)
downloadcoreboot-ef1052918775d321928410aebedeb21ac96b36c0.tar.xz
cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE
Previously, the XIP_ROM_SIZE Kconfig variable is used globally on x86 platforms with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened by not passing '-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage. Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14625 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/Kconfig11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index e80f02b0e1..74d87e2e9f 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -69,8 +69,19 @@ config TSC_SYNC_MFENCE
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.
+config NO_FIXED_XIP_ROM_SIZE
+ bool
+ default n
+ help
+ The XIP_ROM_SIZE Kconfig variable is used globally on x86
+ with the assumption that all chipsets utilize this value.
+ For the chipsets which do not use the variable it can lead
+ to unnecessary alignment constraints in cbfs for romstage.
+ Therefore, allow those chipsets a path to not be burdened.
+
config XIP_ROM_SIZE
hex
+ depends on !NO_FIXED_XIP_ROM_SIZE
default ROM_SIZE if ROMCC
default 0x10000