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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-14 20:06:30 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-14 20:06:30 +0000 |
| commit | 139e6f9555d6ff31c81ff6620bbe6214fa11b1e5 (patch) | |
| tree | 6ff72344e33b5d04c4f33f33b7121cf0e9fba225 /src/cpu | |
| parent | 528b43db32647c10d2d6b16b3585547bf3ab7b03 (diff) | |
| download | coreboot-139e6f9555d6ff31c81ff6620bbe6214fa11b1e5.tar.xz | |
Use symbolic names for some MTRR bits instead of numbers in CAR code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 12 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 12 |
4 files changed, 16 insertions, 16 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 26cdec3fbe..424bd93e7c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -77,7 +77,7 @@ cache_as_ram_setup: /* Check if cpu_init_detected. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(1 << 11), %eax + andl $MTRRdefTypeEn, %eax movl %eax, %ebx /* We store the status. */ jmp_if_k8(CAR_FAM10_out_post_errata) @@ -306,7 +306,7 @@ clear_fixed_var_mtrr_out: jmp_if_k8(wbcache_post_fam10_setup) movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 3949a567c8..fc4eb8ae74 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -354,7 +354,7 @@ lout: */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr /* Enable cache. */ diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index fc4947600f..0ee26fcdd2 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -63,14 +63,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -118,7 +118,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -160,7 +160,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -201,7 +201,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -217,7 +217,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index a1b82675fb..a7605cc689 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -70,14 +70,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -125,7 +125,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -167,7 +167,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -208,7 +208,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -224,7 +224,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) |