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authorStefan Reinauer <stepan@coresystems.de>2010-02-08 12:20:50 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-08 12:20:50 +0000
commit38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 (patch)
treeecb680abac7c73798a4abf5f5733c6ad3e179bb4 /src/cpu
parentd51eddbb6611965165ad72eb3fb04377a51ab64a (diff)
downloadcoreboot-38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0.tar.xz
janitor task: unify and cleanup naming.
cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/dualcore/amd_sibling.c4
-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c2
-rw-r--r--src/cpu/amd/sc520/raminit.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index deaa78cef0..9001ec76a7 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -78,7 +78,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
nb_cfg_54 = read_nb_cfg_54();
#if 0
- //it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
+ //it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it.
if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
//we need to check if e0 single core is there
int i;
@@ -109,7 +109,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
+ printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(nodes);
}
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index defbce2571..822e362a74 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -463,7 +463,7 @@ static void wait_all_core0_started(void)
* start the core0 in node, so it can generate HT packet to feature code.
*
* This function starts the AP nodes core0s. wait_all_core0_started() in
- * cache_as_ram_auto.c waits for all the AP to be finished before continuing
+ * romstage.c waits for all the AP to be finished before continuing
* system init.
*/
static void start_node(u8 node)
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index d20280761d..f52e8fe622 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -89,7 +89,7 @@ void setupsc520(void)
/* as per the book: */
/* PAR register setup */
/* set up the PAR registers as they are on the MSM586SEG */
- /* moved to auto.c by Stepan, Ron says: */
+ /* moved to romstage.c by Stepan, Ron says: */
/* NOTE: move this to mainboard.c ASAP */
setup_pars();