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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-09 02:47:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-24 19:27:43 +0100 |
| commit | 68130f506df5c77107ece8d71aa45b598be77b45 (patch) | |
| tree | fef16b57eadc6b180f97e4c5cc392d195d3cc239 /src/cpu | |
| parent | b174667534c327b8558ff04986a2c1a971b7f04e (diff) | |
| download | coreboot-68130f506df5c77107ece8d71aa45b598be77b45.tar.xz | |
amd/amdfam10: Control Fam15h cache partitioning via nvram
Add options to control cache partitioning and overall memory
performance via nvram.
Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/defaults.h | 5 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 |
2 files changed, 16 insertions, 5 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index d4999b996e..7fd115c93f 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -135,9 +135,8 @@ static const struct { 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, - (0x3 << 20) | (0x1 << 22), 0x00000000, - (0x3 << 20) | (0x1 << 22), 0x00000000}, /* C0 or above [PfcDoubleStride]=1, - PfcStrideMul]=0x3 */ + 1 << 22, 0x00000000, + 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (54-32), diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 55df7a4c03..da458883d3 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -953,6 +953,7 @@ void cpuSetAMDMSR(uint8_t node_id) */ msr_t msr; u8 i; + uint8_t nvram; u32 platform; uint64_t revision; uint8_t enable_c_states; @@ -977,6 +978,13 @@ void cpuSetAMDMSR(uint8_t node_id) /* Revision C0 and above */ if (revision & AMD_OR_C0) { + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); msr = rdmsr(FP_CFG); msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ @@ -996,11 +1004,15 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo &= ~(0x1 << 16); /* DiDtMode */ msr.lo |= ((f3x1fc & 0x1) << 16); wrmsr(FP_CFG, msr); + + if (enable_experimental_memory_speed_boost) { + msr = rdmsr(BU_CFG3); + msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */ + wrmsr(BU_CFG3, msr); + } } #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) - uint8_t nvram; - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(0xc0010055); |