diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-02-14 16:41:54 -0800 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2013-02-16 00:39:01 +0100 |
| commit | 882fdcf2271d385f1110c0f3737ceeb5e30d2861 (patch) | |
| tree | fc01a3aeb727b51e4cabdb4bed5fb2e96a868a70 /src/cpu | |
| parent | 1cf46a7bbf7881275ea74520e9e926abe18e5ffe (diff) | |
| download | coreboot-882fdcf2271d385f1110c0f3737ceeb5e30d2861.tar.xz | |
armv7/exynos5250: fix usage of _stack and _estack
This patch fixes up the usage of stack pointer and regions.
The current approach only works by coincidence, so this fixes a few
things at once to get it into a working state and allow us to use
checkstack() again:
- Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0.
- Assign _stack and _estack using CPU-specific Kconfig variables since
it may reside elsewhere in memory (not necessarily DRAM).
- Make the existing IRAM stack variables more useful in this context.
Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2416
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/samsung/exynos5250/Kconfig | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 2869d7689e..01268e44e5 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -23,7 +23,7 @@ config BL1_SIZE_KB # 0x0202_0000: vendor-provided BL1 # 0x0202_3400: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. -# 0x0207_7f00: stack pointer +# 0x0207_8000: stack pointer # this may be used to calculate offsets config IRAM_BOTTOM @@ -46,6 +46,23 @@ config ROMSTAGE_SIZE hex default 0x10000 +# Stack may reside in either IRAM or DRAM. We will define it to live +# at the top of IRAM for now. +# +# Stack grows downward, push operation stores register contents in +# consecutive memory locations ending just below SP +config STACK_TOP + hex + default 0x02078000 + +config STACK_BOTTOM + hex + default 0x02077000 + +config STACK_SIZE + hex + default 0x1000 + config CBFS_ROM_OFFSET # Calculated by BL1 + max bootblock size. hex "offset of CBFS data in ROM" @@ -73,10 +90,6 @@ config SPI_IMAGE_HACK hex default 0x02060000 -config IRAM_STACK - hex - default 0x02077f00 - # FIXME: other magic numbers that should probably go away config XIP_ROM_SIZE hex |