new cache_as_ram support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 152 insertions, 90 deletions

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index c7de4148a4..1cf141230b 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -1,8 +1,10 @@
 /* by yhlu 6.2005 */
 /* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/
-/* We may need 4K bytes only */
+/* yhlu 2006.3 copy data from cache to ram and reserve 0x1000 for global variables */
 #define CacheSize DCACHE_RAM_SIZE
 #define CacheBase (0xd0000 - CacheSize)
+/* leave some space for global variable to pass to RAM stage */
+#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
@@ -147,7 +149,7 @@ clear_fixed_var_mtrr_out:
 #endif /*USE_FALLBACK_IMAGE == 1*/
 
 	/* set up the stack pointer */
-	movl	$(CacheBase+CacheSize-4), %eax
+	movl	$(CacheBase+CacheSize - 4 - GlobalVarSize), %eax 
 	movl    %eax, %esp
 
 	/* Restore the BIST result */
diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c
new file mode 100644
index 0000000000..593c0ddfd6
--- /dev/null
+++ b/src/cpu/amd/car/clear_init_ram.c
@@ -0,0 +1,59 @@
+/* by yhlu 6.2005 */
+/* be warned, this file will be used core 0/node 0 only */
+
+static void __attribute__((noinline)) clear_init_ram(void)
+{
+	// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
+	// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
+	// so noline clear_init_ram
+        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
+
+}
+
+/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
+static inline __attribute__((always_inline)) void set_init_ram_access(void)
+{
+        __asm__ volatile (
+
+	"pushl %%ecx\n\t"
+	"pushl %%edx\n\t"
+	"pushl %%eax\n\t"
+
+        /* enable caching for first 1M using variable mtrr */
+        "movl    $0x200, %%ecx\n\t"
+        "xorl    %%edx, %%edx\n\t"
+        "movl     $(0 | 6), %%eax\n\t"
+//      "movl     $(0 | MTRR_TYPE_WRBACK), %%eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x201, %%ecx\n\t"
+        "movl    $0x0000000f, %%edx\n\t"
+#if CONFIG_USE_INIT
+        "movl    %%esi, %%eax\n\t"
+#else
+        "movl    $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t"
+#endif
+        "wrmsr\n\t"
+
+#if 0
+        /* enable caching for 64K using fixed mtrr */
+        "movl    $0x26e, %%ecx\n\t"  /* fix4k_f0000*/
+        "movl    $0x1e1e1e1e, %%eax\n\t" /* WB MEM type */
+        "movl    %%eax, %%edx\n\t"
+        "wrmsr\n\t"
+        "movl    $0x26f, %%ecx\n\t" /* fix4k_f8000*/
+        "wrmsr\n\t"
+#endif
+
+	"popl	%%eax\n\t"
+	"popl   %%edx\n\t"
+	"popl	%%ecx\n\t"
+
+        :
+        :
+#if CONFIG_USE_INIT
+        "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800)
+#endif
+        );
+}
+
diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index 55068c5511..68e9e35482 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -37,7 +37,7 @@ static inline void print_debug_cp_run(const char *strval, uint32_t val)
 #endif
 }
 
-static void copy_and_run(unsigned cpu_reset)
+static void copy_and_run(void)
 {
 	uint8_t *src, *dst; 
         unsigned long ilen = 0, olen = 0, last_m_off =  1;
@@ -54,7 +54,7 @@ static void copy_and_run(unsigned cpu_reset)
 		"subl %1, %2\n\t"
 		: "=a" (src), "=b" (dst), "=c" (olen)
 	);
-	memcpy(src, dst, olen);
+	memcpy(dst, src, olen);
 #else 
 
         __asm__ volatile (
@@ -65,14 +65,13 @@ static void copy_and_run(unsigned cpu_reset)
 
 	print_debug_cp_run("src=",(uint32_t)src); 
 	print_debug_cp_run("dst=",(uint32_t)dst);
-	
-//	dump_mem(src, src+0x100);
 
         for(;;) {
                 unsigned int m_off, m_len;
                 while(GETBIT(bb, src, ilen)) {
                         dst[olen++] = src[ilen++];
                 }
+
                 m_off = 1;
                 do {
                         m_off = m_off*2 + GETBIT(bb, src, ilen);
@@ -109,24 +108,13 @@ static void copy_and_run(unsigned cpu_reset)
                 }
         }
 #endif
-//	dump_mem(dst, dst+0x100);
 
 	print_debug_cp_run("linxbios_ram.bin length = ", olen);
 
 	print_debug("Jumping to LinuxBIOS.\r\n");
 
-	if(cpu_reset == 1 ) {
-		__asm__ volatile (
-			"movl $0xffffffff, %ebp\n\t"
-		);
-	}
-	else {
-                __asm__ volatile (
-                        "xorl %ebp, %ebp\n\t"
-                );
-	}
-	
-	__asm__ volatile (
+        __asm__ volatile (
+                "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
 		"cli\n\t"
 		"leal    _iseg, %edi\n\t"
 		"jmp     *%edi\n\t"
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 06a558f413..56e60eefb7 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -3,10 +3,7 @@
 static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 {
         __asm__ volatile (
-	/* 
-	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
-		It is only needed if we want to go back
-	*/
+
         /* We don't need cache as ram for now on */
         /* disable cache */
         "movl    %cr0, %eax\n\t"
@@ -43,5 +40,30 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
         "movl    %cr0, %eax\n\t"
         "andl    $0x9fffffff,%eax\n\t"
         "movl    %eax, %cr0\n\t"
+
         );
 }
+/* be warned, this file will be used core 0 / node 0 and ram stack is ready*/
+
+static void disable_cache_as_ram_bsp(void)
+{
+        __asm__ volatile (
+
+        "pushl	%ecx\n\t"
+        "pushl 	%edx\n\t"
+        "pushl 	%eax\n\t"
+
+	);
+
+	disable_cache_as_ram();
+
+	__asm__ volatile (
+
+        "popl   %eax\n\t"
+        "popl   %edx\n\t"
+        "popl   %ecx\n\t"
+
+        );
+}
+
+
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 345e4c34b0..0a91326b85 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,7 +1,9 @@
-
+/* 2005.6 by yhlu 
+ * 2006.3 yhlu add copy data from CAR to ram
+ */
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
-#include "cpu/amd/car/clear_1m_ram.c"
+#include "cpu/amd/car/clear_init_ram.c"
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
@@ -12,11 +14,18 @@ static inline void print_debug_pcar(const char *strval, uint32_t val)
 #endif
 }
 
-
-
-static void post_cache_as_ram(unsigned cpu_reset)
+static void inline __attribute__((always_inline))  memcopy(void *dest, const void *src, unsigned long bytes)
 {
+        __asm__ volatile(
+                "cld\n\t"
+                "rep movsl\n\t"
+                : /* No outputs */
+                : "S" (src), "D" (dest), "c" ((bytes)>>2)
+                );
+}
 
+static void post_cache_as_ram(void)
+{
 
 #if 1
         {
@@ -30,60 +39,50 @@ static void post_cache_as_ram(unsigned cpu_reset)
         }
 #endif
 
-        print_debug_pcar("cpu_reset = ",cpu_reset);
+	unsigned testx = 0x5a5a5a5a;
+	print_debug_pcar("testx = ", testx);
 
-        if(cpu_reset == 0) {
-                print_debug("Clearing initial memory region: ");
-        }
-        print_debug("No cache as ram now - ");
+	/* copy data from cache as ram to 
+		ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead.
+	 */
+#if CONFIG_LB_MEM_TOPK <= 1024
+        #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
+#endif
+	
+	set_init_ram_access();
 
-        /* store cpu_reset to ebx */
+	print_debug("Copying data from cache to ram -- switching to use ram as stack... ");
+
+	/* from here don't store more data in CAR */
         __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
+        	"pushl  %eax\n\t"
         );
-
-	disable_cache_as_ram();
-
-        if(cpu_reset==0) { // cpu_reset don't need to clear it 
-		clear_1m_ram();
-        }
-	else {
-		set_1m_ram();
-	}
-
+        memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
         __asm__ volatile (
                 /* set new esp */ /* before _RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+        ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
+        __asm__ volatile (
+	        "popl   %eax\n\t"
         );
+	/* We can put data to stack again */
 
-        {
-                unsigned new_cpu_reset;
-
-                /* get back cpu_reset from ebx */
-                __asm__ volatile (
-                        "movl %%ebx, %0\n\t"
-                        :"=a" (new_cpu_reset)
-                );
-
-                print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
+        /* only global variable sysinfo in cache need to be offset */
+        print_debug("Done\r\n");
+        print_debug_pcar("testx = ", testx);
 
-                if(new_cpu_reset==0) {
-                        print_debug("done\r\n");
-                } else
-                {
-                        print_debug("\r\n");
-                }
+	print_debug("Disabling cache as ram now \r\n");
+	disable_cache_as_ram_bsp();  
 
-                print_debug_pcar("new_cpu_reset = ", new_cpu_reset);
+        print_debug("Clearing initial memory region: ");
+        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram
+        print_debug("Done\r\n");
 
-
-                /*copy and execute linuxbios_ram */
-                copy_and_run(new_cpu_reset);
-                /* We will not return */
-        }
+        /*copy and execute linuxbios_ram */
+        copy_and_run();
+        /* We will not return */
 
 	print_debug("should not be here -\r\n");
 
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 6a070d56ec..e60aa35bf9 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -1,7 +1,6 @@
 //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
 #ifndef K8_SET_FIDVID
 	#define K8_SET_FIDVID 0
-	
 #endif
 
 #ifndef K8_SET_FIDVID_CORE0_ONLY
@@ -42,7 +41,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t p
                 j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
                 if(nb_cfg_54) {
  	               if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation 
-        	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
+       	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
                        } 
                        if(e0_later_single_core) {
                                 j=1;
@@ -204,7 +203,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 		/* get the apicid, it may be lifted already */
 		apicid = lapicid();
 
-#if 1 
+#if 0 
 		// show our apicid, nodeid, and coreid
 		if( id.coreid==0 ) {
 			if (id.nodeid!=0) //all core0 except bsp
@@ -219,21 +218,9 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 #endif
 
                 if (cpu_init_detectedx) {
-		#if RAMINIT_SYSINFO == 1
-			//We need to init sblnk and sbbusn, because it is called before ht_setup_chains_x
-		        sysinfo->sblnk = get_sblnk();
-			sysinfo->sbbusn = node_link_to_bus(0, sysinfo->sblnk);
-		#endif
-			print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detect from ");
-
-			print_debug("\r\nIssuing SOFT_RESET...\r\n");
-
-			#if RAMINIT_SYSINFO == 1
-                        soft_reset(sysinfo);
-			#else
-			soft_reset();
-			#endif
-
+                        print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from ");
+                        print_debug("\r\nIssuing SOFT_RESET...\r\n");
+                        soft_reset();
                 }
 
 		if(id.coreid==0) {
@@ -256,8 +243,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 			wait_cpu_state(bsp_apicid, 0x44);
 			lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
 
+			set_init_ram_access(); //inline
 			disable_cache_as_ram(); // inline
-			set_1m_ram(); // inline
                         stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... 
                 }
 
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index d7f7124deb..279101b74b 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -25,7 +25,7 @@
  */ 
 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
 {
-	return (unsigned long)orig_start_eip & 0xfffff; // 20 bit 
+	return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 
 }
 
 static void copy_secondary_start_to_1m_below(void) 
@@ -43,7 +43,7 @@ static void copy_secondary_start_to_1m_below(void)
         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
 
         /* copy the _secondary_start to the ram below 1M*/
-        memcpy(start_eip, (unsigned long)_secondary_start, code_size);
+        memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
 
         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
 #endif
@@ -117,7 +117,12 @@ static int lapic_start_cpu(unsigned long apicid)
 		return 0;
 	}
 
+#if _RAMBASE >= 0x100000
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
+#else
+	start_eip = (unsigned long)_secondary_start;
+#endif
+
 	printk_debug("start_eip=0x%08lx\n", start_eip);
        
 	num_starts = 2;