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authorLi-Ta Lo <ollie@lanl.gov>2004-11-04 18:36:06 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-11-04 18:36:06 +0000
commitf84926efca2f871fa557cccee36f0f773ec7190b (patch)
tree669414cbe6344aa61839f37422c0e163eae4f0fa /src/cpu
parent1995f1af35b53b5c07694df7296f5eb20461b1c6 (diff)
downloadcoreboot-f84926efca2f871fa557cccee36f0f773ec7190b.tar.xz
tell people that the segment descriptors are different for ROMCC and
GCC code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/16bit/entry16.inc8
-rw-r--r--src/cpu/x86/32bit/entry32.inc9
-rw-r--r--src/cpu/x86/lapic/secondary.S2
3 files changed, 11 insertions, 8 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 61726d8ad9..674315fbd2 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -108,10 +108,10 @@ _start:
/* Now that we are in protected mode jump to a 32 bit code segment. */
data32 ljmp $ROM_CODE_SEG, $__protected_start
-/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
- * at 0x18; these are Linux-compatible.
- */
-
+ /**
+ * The gdt is defined in entry32.inc, it has a 4 Gb code segment
+ * at 0x08, and a 4 GB data segment at 0x10;
+ */
.align 4
.globl gdtptr16
gdtptr16:
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 3d30a3f85f..724aed32eb 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -8,17 +8,20 @@
.align 4
.globl gdtptr
+ /* This is the gdt for ROMCC/ASM part of LinuxBIOS.
+ * It is different from the gdt in GCC part of LinuxBIOS
+ * which is defined in c_start.S */
gdt:
gdtptr:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
.word 0
-/* flat code segment */
+ /* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
-
-/* flat data segment */
+
+ /* selgdt 0x10,flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 5185021c3c..b212f43b38 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -26,7 +26,7 @@ _secondary_start:
orl $0x60000001, %eax /* CD, NW, PE = 1 */
movl %eax, %cr0
- ljmpl $0x10, $1f
+ ljmpl $0x10, $1f
1:
.code32
movw $0x18, %ax