diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-25 11:47:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-03 13:32:19 +0000 |
| commit | 99f1d5033591a28bf6b6a142adc24b285abc7870 (patch) | |
| tree | 37a218c272ee8abcb4edd48307642324225f429a /src/cpu | |
| parent | 4be1f8a2f6be29e7a9983d068c2356b7728f91d5 (diff) | |
| download | coreboot-99f1d5033591a28bf6b6a142adc24b285abc7870.tar.xz | |
cpu/amd/family_10h-family_15h: Remove variable set but not used
Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33006
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 310706ba95..d6a4725e2e 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -986,7 +986,6 @@ void cpuSetAMDMSR(uint8_t node_id) uint8_t nvram; u32 platform; uint64_t revision; - uint8_t enable_c_states; uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1062,21 +1061,16 @@ void cpuSetAMDMSR(uint8_t node_id) } if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - enable_c_states = 0; if (CONFIG(HAVE_ACPI_TABLES)) - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (enable_c_states) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } + if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && + (nvram)) { + /* Set up the C-state base address */ + msr_t c_state_addr_msr; + c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); + c_state_addr_msr.lo = ACPI_CPU_P_LVL2; + wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); + } } -#else - enable_c_states = 0; #endif if (revision & AMD_FAM15_ALL) { |