cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE

AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the
romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol.

Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

9 files changed, 2 insertions, 50 deletions

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index f21bf5467f..b1fde2dcf7 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -28,20 +28,10 @@ config CPU_AMD_AGESA
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
+	select NO_FIXED_XIP_ROM_SIZE
 
 if CPU_AMD_AGESA
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-	help
-	  Overwride the default write through caching size as 1M Bytes.
-	  On some AMD platforms, one socket supports 2 or more kinds of
-	  processor family, compiling several CPU families agesa code
-	  will increase the romstage size.
-	  In order to execute romstage in place on the flash ROM,
-	  more space is required to be set as write through caching.
-
 config UDELAY_LAPIC_FIXED_FSB
 	int
 	default 200
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index 4fc2ba076c..0324d129a3 100644
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-
 endif
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index adbe7fdb76..518235b12c 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
 	int
 	default 36
 
-config XIP_ROM_SIZE
-	hex
-	default 0x80000
-
 endif
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index fde1adf118..93e9ab26ae 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
 endif
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index 9fef94d327..e87a2d4e42 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -21,10 +21,6 @@ config CPU_ADDR_BITS
 	int
 	default 40
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
 config FORCE_AM1_SOCKET_SUPPORT
 	bool
 	default n
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
index e5e27b55b4..37025ab4bf 100644
--- a/src/cpu/amd/pi/00630F01/Kconfig
+++ b/src/cpu/amd/pi/00630F01/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
 endif
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
index 647044843a..374672da03 100644
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ b/src/cpu/amd/pi/00660F01/Kconfig
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
 endif
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index 43abc80aba..7ba49439eb 100644
--- a/src/cpu/amd/pi/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -23,8 +23,4 @@ config CPU_ADDR_BITS
 	int
 	default 40
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
 endif
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 973a086e9f..b33302ecef 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -28,23 +28,13 @@ config CPU_AMD_PI
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
 	select SMM_ASEG
+	select NO_FIXED_XIP_ROM_SIZE
 
 if CPU_AMD_PI
 
 config BINARYPI_LEGACY_WRAPPER
 	def_bool n
 
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-	help
-	  Overwride the default write through caching size as 1M Bytes.
-	  On some AMD platforms, one socket supports 2 or more kinds of
-	  processor family, compiling several CPU families agesa code
-	  will increase the romstage size.
-	  In order to execute romstage in place on the flash ROM,
-	  more space is required to be set as write through caching.
-
 config UDELAY_LAPIC_FIXED_FSB
 	int
 	default 200