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authorKane Chen <kane.chen@intel.com>2014-10-01 11:13:54 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-03-09 03:33:13 +0100
commit18cb1340f185150b9708257ba8024b6900706083 (patch)
tree0d567633540e19104711d664b44f144ba653ec25 /src/device/Kconfig
parent2c4aab3fd6cd7b357b8389c20a95a6ad59cc75a0 (diff)
downloadcoreboot-18cb1340f185150b9708257ba8024b6900706083.tar.xz
device/pciexp: Add support for PCIe CLK power management
Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> [Edit commit message.] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/device/Kconfig')
-rw-r--r--src/device/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 91da02a193..42a68d296a 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -251,6 +251,14 @@ config PCIEXP_ASPM
help
Detect and enable ASPM on PCIe links.
+config PCIEXP_CLK_PM
+ prompt "Enable PCIe Clock Power Management"
+ bool
+ depends on PCIEXP_PLUGIN_SUPPORT
+ default n
+ help
+ Detect and enable Clock Power Management on PCIe.
+
config PCI_BUS_SEGN_BITS
int
default 0