summaryrefslogtreecommitdiff
path: root/src/device/azalia_device.c
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@chromium.org>2017-10-25 09:47:58 -0700
committerFurquan Shaikh <furquan@google.com>2017-10-25 17:06:06 +0000
commitaf8839888758d25943fbc64eea29b18634a41c4f (patch)
tree0859f521796aa18cc8f81790a5cc643b8f18ac29 /src/device/azalia_device.c
parent74d8ed0cb8c659ec65b509bc32882e194168a891 (diff)
downloadcoreboot-af8839888758d25943fbc64eea29b18634a41c4f.tar.xz
soc/intel/skylake: Fix broken GNVS offset for chromeos
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX ASL) added new GNVS variables but did not adjust the unused array size and thus broke chromeos offset. This change fixes the above issue by reducing the size of unused array. BUG=b:68254376 TEST=Verified that chromeos offset is correct. crossystem is able to read all variables. Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/azalia_device.c')
0 files changed, 0 insertions, 0 deletions