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author | Thaminda Edirisooriya <thaminda@google.com> | 2015-08-26 15:28:04 -0700 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-09-10 17:23:45 +0000 |
commit | b094583c6fd9d330be28ed6feb1c1140de07ff37 (patch) | |
tree | 57cb30a458d5bc1434ee530f31bc65a192d9e209 /src/device/cpu_device.c | |
parent | 87582d1cf2ff09c5ef7f48f41469eaf124e9ffde (diff) | |
download | coreboot-b094583c6fd9d330be28ed6feb1c1140de07ff37.tar.xz |
riscv-virtual-memory: Add virtual memory setup
Execution in supervisor level code in RISCV requires early setup of
virtual memory. Add initialization calls in
src/arch/riscv/virtual_memory.c to implement the required page table
setup, and helper functions to use when jumping to the payload correctly
in riscv.
Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/device/cpu_device.c')
0 files changed, 0 insertions, 0 deletions