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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-05 16:40:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-05 11:41:52 +0200
commit36abdc4017d93484577fe08fdb61d8ff22c6259c (patch)
treeb1f84b1c8006ca0952e22880e92b1e8a55bafffa /src/device/dram
parent93d9f92cfbb214718e211aee71ac869c77f725ee (diff)
downloadcoreboot-36abdc4017d93484577fe08fdb61d8ff22c6259c.tar.xz
gizmosphere/gizmo: Move support of SPD data in CBFS
This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/device/dram')
-rw-r--r--src/device/dram/Makefile.inc1
-rw-r--r--src/device/dram/spd_cache.c68
2 files changed, 69 insertions, 0 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
new file mode 100644
index 0000000000..05f440b3b7
--- /dev/null
+++ b/src/device/dram/Makefile.inc
@@ -0,0 +1 @@
+romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c
new file mode 100644
index 0000000000..0032f327dd
--- /dev/null
+++ b/src/device/dram/spd_cache.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <device/dram/ddr3.h>
+#include <spd_cache.h>
+#include <stdint.h>
+#include <string.h>
+
+#define SPD_SIZE 128
+#define SPD_CRC_HI 127
+#define SPD_CRC_LO 126
+
+int read_spd_from_cbfs(u8 *buf, int idx)
+{
+ const char *spd_file;
+ size_t spd_file_len = 0;
+ size_t min_len = (idx + 1) * SPD_SIZE;
+
+ printk(BIOS_DEBUG, "read SPD\n");
+ spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
+ &spd_file_len);
+ if (!spd_file)
+ printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
+ if (spd_file_len < min_len)
+ printk(BIOS_EMERG, "Missing SPD data.");
+ if (!spd_file || spd_file_len < min_len)
+ return -1;
+
+ memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE);
+
+ u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE);
+
+ if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
+ || (buf[SPD_CRC_LO] != (crc & 0xff))
+ || (buf[SPD_CRC_HI] != (crc >> 8))) {
+ printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
+ buf[SPD_CRC_LO] = crc & 0xff;
+ buf[SPD_CRC_HI] = crc >> 8;
+ u16 i;
+ printk(BIOS_WARNING, "\nDisplay the SPD");
+ for (i = 0; i < SPD_SIZE; i++) {
+ if((i % 16) == 0x00)
+ printk(BIOS_WARNING, "\n%02x: ", i);
+ printk(BIOS_WARNING, "%02x ", buf[i]);
+ }
+ printk(BIOS_WARNING, "\n");
+ }
+ return 0;
+}