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| author | Patrick Georgi <pgeorgi@chromium.org> | 2017-01-28 15:26:43 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-02-10 18:04:11 +0100 |
| commit | 2e08b59cdcf9a26ae9e6d4107be8e45a5fb9dbdf (patch) | |
| tree | 243c5faab07837153940f6c208f39e665886f342 /src/device/dram | |
| parent | ded1e05d11675d899e07906e04032b3cc2f29711 (diff) | |
| download | coreboot-2e08b59cdcf9a26ae9e6d4107be8e45a5fb9dbdf.tar.xz | |
ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18264
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/device/dram')
| -rw-r--r-- | src/device/dram/spd_cache.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 3bdd9c19dd..a74e4a77ba 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -22,13 +22,14 @@ #include <string.h> #define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 _Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); -int read_spd_from_cbfs(u8 *buf, int idx) +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + const char *spd_file; size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; |