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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-08 18:14:34 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-11 11:34:37 +0000
commit8a41f4b71e883ec66be511cb592ee19dfa6708c5 (patch)
treed0f7d8e47ed1dbe3b27038a0232f89aaff8d261d /src/device/pci_early.c
parent5b14116a04b4b96d25f825bef8f34caf4bd51466 (diff)
downloadcoreboot-8a41f4b71e883ec66be511cb592ee19dfa6708c5.tar.xz
device/pci_ops: Move questionable pci_locate() variants
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>. There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/device/pci_early.c')
-rw-r--r--src/device/pci_early.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/device/pci_early.c b/src/device/pci_early.c
index 9086e64b85..ea2ebd5033 100644
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@@ -165,3 +165,34 @@ void pci_early_bridge_init(void)
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
}
+
+/* FIXME: A lot of issues using the following, please avoid.
+ * Assumes 256 PCI busses, scans them all even when PCI bridges are still
+ * disabled. Probes all functions even if 0 is not present.
+ */
+pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+{
+ for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
+ unsigned int id;
+ id = pci_read_config32(dev, 0);
+ if (id == pci_id)
+ return dev;
+ }
+ return PCI_DEV_INVALID;
+}
+
+pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
+{
+ pci_devfn_t dev, last;
+
+ dev = PCI_DEV(bus, 0, 0);
+ last = PCI_DEV(bus, 31, 7);
+
+ for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
+ unsigned int id;
+ id = pci_read_config32(dev, 0);
+ if (id == pci_id)
+ return dev;
+ }
+ return PCI_DEV_INVALID;
+}