diff options
| author | Martin Roth <martin@coreboot.org> | 2019-10-23 21:41:00 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-10-27 21:08:39 +0000 |
| commit | 38ddbfb325866716c9c65a460e388f33d1a773dd (patch) | |
| tree | ffc7469c60e0a94321cf96de2bd0c4928067849f /src/device/pciexp_device.c | |
| parent | e74ca4ffc2008a93e38909a4d583408affbaf28a (diff) | |
| download | coreboot-38ddbfb325866716c9c65a460e388f33d1a773dd.tar.xz | |
src/[arch-lib]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/device/pciexp_device.c')
| -rw-r--r-- | src/device/pciexp_device.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 71702a7360..72aac4c7c5 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -45,7 +45,7 @@ unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap) * Re-train a PCIe link */ #define PCIE_TRAIN_RETRY 10000 -static int pciexp_retrain_link(struct device *dev, unsigned cap) +static int pciexp_retrain_link(struct device *dev, unsigned int cap) { unsigned int try; u16 lnk; @@ -90,8 +90,8 @@ static int pciexp_retrain_link(struct device *dev, unsigned cap) * and enable Common Clock Configuration if possible. If CCC is * enabled the link must be retrained. */ -static void pciexp_enable_common_clock(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap) +static void pciexp_enable_common_clock(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) { u16 root_scc, endp_scc, lnkctl; @@ -122,7 +122,7 @@ static void pciexp_enable_common_clock(struct device *root, unsigned root_cap, } } -static void pciexp_enable_clock_power_pm(struct device *endp, unsigned endp_cap) +static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) { /* check if per port clk req is supported in device */ u32 endp_ca; @@ -328,8 +328,8 @@ static void pciexp_config_L1_sub_state(struct device *root, struct device *dev) * by checking both root port and endpoint and returning * the highest latency value. */ -static int pciexp_aspm_latency(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap, +static int pciexp_aspm_latency(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap, enum aspm_type type) { int root_lat = 0, endp_lat = 0; @@ -364,8 +364,8 @@ static int pciexp_aspm_latency(struct device *root, unsigned root_cap, /* * Enable ASPM on PCIe root port and endpoint. */ -static void pciexp_enable_aspm(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap) +static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) { const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; enum aspm_type apmc = PCIE_ASPM_NONE; |