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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-02 08:56:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 13:00:56 +0100
commite25b5ef39fd10e48e87e0c4770a721a786e36a36 (patch)
tree113c2b4eba9bf7fddd6badbafc3c0f6ac0cef04f /src/device
parent3d15e10aef5811e8c7146e5defb0e36b848547ed (diff)
downloadcoreboot-e25b5ef39fd10e48e87e0c4770a721a786e36a36.tar.xz
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/device_util.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/device/device_util.c b/src/device/device_util.c
index 56afefdc87..157f7b7443 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -888,6 +888,26 @@ void fixed_mem_resource(device_t dev, unsigned long index,
resource->flags |= type;
}
+void mmconf_resource_init(struct resource *resource, resource_t base,
+ int buses)
+{
+ resource->base = base;
+ resource->size = buses * MiB;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR "
+ "0x%08lx-0x%08lx.\n", (unsigned long)(resource->base),
+ (unsigned long)(resource->base + resource->size));
+}
+
+void mmconf_resource(struct device *dev, unsigned long index)
+{
+ struct resource *resource = new_resource(dev, index);
+ mmconf_resource_init(resource, CONFIG_MMCONF_BASE_ADDRESS,
+ CONFIG_MMCONF_BUS_NUMBER);
+}
+
void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;