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authorNico Huber <nico.h@gmx.de>2021-03-06 14:13:58 +0100
committerNico Huber <nico.h@gmx.de>2021-03-12 23:44:49 +0000
commita768deae7346c5de740723331e3eb5ee04746bfe (patch)
treed96270ac5f62f957f2848291676954d2611898b7 /src/device
parent2d24146aef39ef5a6b1d061a81c8c9e333886b5c (diff)
downloadcoreboot-a768deae7346c5de740723331e3eb5ee04746bfe.tar.xz
device: Give `pci_ops.set_L1_ss_latency` a proper name
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/pciexp_device.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 8d4bb9849d..3153e0eb37 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -132,8 +132,8 @@ static void pciexp_config_max_latency(struct device *root, struct device *dev)
unsigned int cap;
cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
if ((cap) && (root->ops->ops_pci != NULL) &&
- (root->ops->ops_pci->set_L1_ss_latency != NULL))
- root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
+ (root->ops->ops_pci->set_ltr_max_latencies != NULL))
+ root->ops->ops_pci->set_ltr_max_latencies(dev, cap + 4);
}
static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap)