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| author | Nico Huber <nico.h@gmx.de> | 2021-03-07 00:29:20 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-12 23:44:57 +0000 |
| commit | c2ffe89f777dfd85308177e126b22f10ef5c2e0a (patch) | |
| tree | 59d5f8054cb7c0ded8a247c2233e4a42e84bb4c1 /src/device | |
| parent | a768deae7346c5de740723331e3eb5ee04746bfe (diff) | |
| download | coreboot-c2ffe89f777dfd85308177e126b22f10ef5c2e0a.tar.xz | |
pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper
Replace the existing, odd looking, unordered definitions used for
LTR configuration with the usual names used by upstream libpci.
TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.
Fixes: Code looked like UEFI copy-pasta. Header file was a mess.
Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/pciexp_device.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 3153e0eb37..0b7c649d93 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -140,9 +140,9 @@ static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap) { unsigned int val; - val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET); + val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2); - if (val & LTR_MECHANISM_SUPPORT) + if (val & PCI_EXP_DEVCAP2_LTR) return true; return false; @@ -164,10 +164,10 @@ static void pciexp_configure_ltr(struct device *dev) return; } - cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET; + cap += PCI_EXP_DEVCTL2; /* Enable LTR for device */ - pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN); + pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR); /* Configure Max Snoop Latency */ pciexp_config_max_latency(dev->bus->dev, dev); |