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| author | Furquan Shaikh <furquan@google.com> | 2020-03-12 17:51:24 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-12 19:44:03 +0000 |
| commit | 871baf2230dc1e0ed2becfd8526e00d5367618b3 (patch) | |
| tree | cfacc09ac0e78bae9280a1af0c69310348917ab2 /src/device | |
| parent | 44ae0eacb82259243bf844a3fe5ad24a7821e997 (diff) | |
| download | coreboot-871baf2230dc1e0ed2becfd8526e00d5367618b3.tar.xz | |
pci_device: Extend PCI domain limit to 64-bit
This change updates the resource limit for PCI domain to allow
resource allocation above 4G boundary. The resource limit is set to
the highest physical address for the CPU.
BUG=b:149186922
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idfcc9a390d309886ee2b7880b29502c740e6578e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39488
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/pci_device.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 9036f53f3b..2c08ebc72e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -9,6 +9,7 @@ #include <device/pci_ops.h> #include <bootmode.h> #include <console/console.h> +#include <cpu/cpu.h> #include <stdlib.h> #include <stdint.h> #include <string.h> @@ -433,7 +434,7 @@ void pci_domain_read_resources(struct device *dev) /* Initialize the system-wide memory resources constraints. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->limit = 0xffffffffULL; + res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } |