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| author | Patrick Georgi <pgeorgi@chromium.org> | 2017-01-28 13:12:09 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-02-10 17:57:15 +0100 |
| commit | 44a46a1f041ad7101cfe3c2dcb94b1406bd4246b (patch) | |
| tree | 3a33fa261fad718106ff8853a958f989ed2f3209 /src/device | |
| parent | d09dc6b442415d3dd0753483e4d4d72ce26ce56e (diff) | |
| download | coreboot-44a46a1f041ad7101cfe3c2dcb94b1406bd4246b.tar.xz | |
device/dram: use global DIMM_SPD_SIZE Kconfig variable
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/dram/spd_cache.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index c7dd97dc8f..3bdd9c19dd 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -25,11 +25,13 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126 +_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); + int read_spd_from_cbfs(u8 *buf, int idx) { const char *spd_file; size_t spd_file_len = 0; - size_t min_len = (idx + 1) * SPD_SIZE; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); @@ -40,9 +42,9 @@ int read_spd_from_cbfs(u8 *buf, int idx) if (!spd_file || spd_file_len < min_len) return -1; - memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) @@ -53,7 +55,7 @@ int read_spd_from_cbfs(u8 *buf, int idx) buf[SPD_CRC_HI] = crc >> 8; u16 i; printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { if((i % 16) == 0x00) printk(BIOS_WARNING, "\n%02x: ", i); printk(BIOS_WARNING, "%02x ", buf[i]); |