diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-24 20:34:57 -0500 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2015-10-25 04:47:10 +0100 |
| commit | 7d8a478e706aae6b4806d2f00d58181e11642277 (patch) | |
| tree | cdbb78f9e22d751255363cf954d3757e79e4ec49 /src/device | |
| parent | d657446884858ff11b08efbe35921c0b2b49f066 (diff) | |
| download | coreboot-7d8a478e706aae6b4806d2f00d58181e11642277.tar.xz | |
device/pci_device: Set bridge primary bus number before scanning
Certain devices, such as the Intel 82575GB, contain multiple nested
PCIe bridges (for example the PES12N3A). Coreboot does not set
the primary bus number of the lower bridges, causing upstream
forwarding failure. This in turn causes coreboot to fail to find
the lowest devices (in this case the NICs), and as a result the
required resources are not allocated and the NICs do not function.
Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12186
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/pci_device.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index cf2f74f81a..51232298c6 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1180,6 +1180,7 @@ static void pci_bridge_route(struct bus *link, scan_state state) if (state == PCI_ROUTE_CLOSE) { buses |= 0xfeff << 8; } else if (state == PCI_ROUTE_SCAN) { + buses |= parent->secondary & 0xff; buses |= ((u32) link->secondary & 0xff) << 8; buses |= 0xff << 16; /* MAX PCI_BUS number here */ } else if (state == PCI_ROUTE_FINAL) { |